This invention relates to a converter which is constructed of a plurality of insulated-gate field effect transistors (hereinbelow, abbreviated to "FETs") put into a semiconductor integrated circuit device, and more particularly to a converter which is used as a digital-to-analog converter (hereinafter, abbreviated to "DAC") or an analog-to-digital converter (hereinafter, abbreviated to "ADC").
A converter which employs FETs as voltage switching elements has been known from, for example, the official gazette of Japanese laid-open patent publication No. 52-28851.
In this known converter, a plurality of P-channel type FETs (hereinbelow, termed "P-type FETs") formed on a single semiconductor substrate are connected in the shape of a tree between a plurality of input points and one output point and are controlled "on" and "off" by a digital signal having a plurality of bits.
By the switching control of the plurality of P-type FETs, one of the plurality of input points as corresponds to the state of the digital signal is coupled to the output point. The respective input points are supplied with voltages of levels different from one another from a resistance voltage divider which divides a reference voltage. Therefore, a voltage of a level corresponding to the state of the digital signal is provided at the output point.
According to the above converter, however, the level of the voltage to be delivered to the output point is limited as will be explained below.
An FET must have its gate potential raised greater than its threshold voltage (hereinafter, termed "V.sub.th ") with respect to its source potential in order to bring it into the "on" state. Accordingly, in case of using the P-type FET as described above, the upper limit of the selectible voltages is restricted by the V.sub.th as well as the level of the digital signal to be impressed on the gate of the P-type FET.
The respective P-type FETs formed on the single semiconductor substrate as described above have a bias voltage (hereinbelow, termed "back gate bias voltage") applied from the semiconductor substrate which serves as a common substrate gate. As a result, the V.sub.th of each P-type FET has its level increased by the known substrate effect.
In such case where the semiconductor substrate is maintained at the ground potential of the circuit, the back gate bias voltage is formed of the potentials of the source, drain and channel of the P-type FET. Therefore, the P-type FET for switching a voltage of a level great in the absolute value receives a back gate bias voltage of a great level corresponding thereto and accordingly has its V.sub.th made great. Usually, an FET of great V.sub.th comes to exhibit a comparatively great drain--source resistance under a constant gate bias voltage.
Thus, according to the converter as described above, the voltage which can be delivered to the output point has its level limited, not only by the V.sub.th of the FET and the digital signal level as stated previously, but also by the attenuation induced by the increased drain-source resistance of the FET. In other words, it is difficult with such converter to deliver a voltage of a desirable level corresponding to the digital signal.
In order to eliminate the limitations to the output voltage level as described above, the digital signal level for controlling the plurality of P-type FETs "on" and "off" can be increased by employing, for example, a voltage booster circuit. In this case, however, circuit elements for constructing the voltage booster circuit are required.